Most general-purpose digital computers provide a system for detecting and handling single-bit or multiple-bit parity errors. The occurrence of soft errors is not uncommon when data signals are being read from storage devices such as static random access memories (SRAMs) and dynamic random access memories (DRAMs). This is especially true when high-density memories are employed, as is generally the case in large data processing systems.
In one example, the presence of alpha and other particles can cause soft parity errors in static random access memories (SRAMs) and dynamic random access memories (DRAMs). Alpha particles are randomly generated, positively charged nuclear particles originating from several sources, including cosmic rays that come from outer space and constantly bombard the earth, and from the decay of natural occurring radioisotopes like Radon, Thorium, and Uranium. Concrete buildings, and lead based products such as solder, paint, ceramics, and some plastics are all well-known alpha emitters. Especially smaller geometry storage devices can be adversely affected by the emission of alpha and other particles, causing a higher occurrence of soft parity errors.
As discussed above, storage devices such as any type of RAM are susceptible to the types of error conditions discussed above. This includes control store RAMs of the type often employed to control logic sequencers within data processing systems. It is common, for example, to utilize one or more control store RAMs to control various logic sections of an instruction processor. For instance, consider an instruction decode circuit that is designed to decode an instruction opcode in preparation for instruction execution. The decode circuit may include a control store RAM that stores control signals that may be employed as decoded instruction signals. Specifically, the opcode may be presented as an address to a control store RAM. Data read from the control store RAM may then be used as the decoded instruction to control further instruction execution.
Using control store RAMs in the foregoing manner adds flexibility to a logic design. Control over the hardware can be altered by simply modifying the data stored within the RAMs. As is known in the art, this can be accomplished using a serial scan-set interface, for example. This may allow a logic designer to readily add unforeseen changes and/or correct design errors or oversights. However, as discussed above, these types of devices are often prone to parity errors.
One way to detect parity errors is through the use of parity bits, as is known in the art. In some cases, a detected error is reported to a maintenance processor, operating system, or other error-handling system, which in the case of a control store RAM, often results in a critical error that halts the execution of the data processing system, and often requires a maintenance technician, or in some cases, a specialized operating system routine, to help diagnose and fix the problem. This can bring the system down for some time, which can result in inefficient use of the data processing system resource. What is needed, therefore, is an improved system and method for detecting and then correcting errors in a control store RAM.